Integrated analog source driver for active matrix liquid crystal display

ABSTRACT

A source driver for an active matrix liquid crystal display, comprising a sample-and-hold circuit for sampling successive lines of an input video signal, a source follower for applying successive lines of the input video signal sampled by the sample-and-hold circuit to successive source lines of the active matrix crystal display, the source follower being characterized by a predetermined threshold voltage; a reset circuit for resetting the successive source lines after respective ones of the successive lines of the input video signal; and an autozero circuit for cancelling the threshold voltage from the video signal so that variations in the threshold voltage do not affect the video signal applied to the successive source lines.

FIELD OF THE INVENTION

This invention relates generally to active-matrix liquid crystaldisplays (AMLCDs), and more particularly to an analog source driverintegrated directly on an AMLCD.

BACKGROUND OF THE INVENTION

Silicon integrated circuits are well known in the art for driving LCDs.Prior art drivers which are fabricated separately from the LCD may bemanufactured with transistor characteristics which can be matchedreasonably well, and operational amplifier type feedback circuitry canbe used to reduce the gain and offset variations between channels.

It is also known in the prior art to incorporate drivers for AMLCDsdirectly on the LCD glass. Integral drivers have been designed in aneffort to eliminate expensive prior art separate driver integratedcircuits (ICs) and unreliable edge interconnections between the driversand AMLCDs, thereby reducing overall system cost and size of the opticalheads incorporating the AMLCDs.

However, it is not a simple matter to design such integrated driverssince it is difficult to manufacture TFT operational amplifiers as theoutput stages would be required to consist of plural TFTs connected inseries across the power rails. It would not be possible to prevent allof the series pairs of TFTs on such an integrated driver from conductingsimultaneously. This would result in non-uniformity and poor performancein some cases would short circuit the power supply.

There have been several approaches suggested in the prior art for thedesign of integrated TFT (Thin Film Transistor) gate drivers. A gatedriver functions basically as a shift register. Consequently, prior artintegrated gate drivers have been designed using drain clockingcircuitry for achieving low power dissipation in NMOS CdSe TFTscomparable to that normally associated with CMOS devices. One such priorart driver is set forth in an article of Schleupen, K., et al. entitled"An Integrated 4-bit Gray-Scale Column Driver for TV AMLCDs", 1994 SIDDigest (Society for Information Display).

However, there has been less progress in the prior art toward aconsensus on the design of TFT source drivers for AMLCDs. Indeed, thereare presently two distinct approaches to the design of source drivers:digital and analog. Existing digital source drivers are known forproviding multiple bit outputs (eg. a 4 bit digital driver can beimplemented using four large capacitors and 21 TFTs), which aresufficient for low amplitude resolution applications such as aircraftinstruments or simple on/off checklist displays. Although digitaldrivers are expandable to a larger number of bits, the device sizeapproximately doubles for each added bit. By way of contrast, a singleanalog driver can be designed which is suitable for any size of display.Such a design should utilize no resistors, should be capable ofimplementation in NMOS enhancement mode and must be compatible with theactive matrix TFTs (ie. identical thickness of semiconductor material).

A source driver comprises three basic functional blocks: an input videomultiplexer, a storage device, and an output drive stage. The inputvideo multiplexer and storage device may be connected in series or mayeffectively be connected in parallel if a double bufferedsample-and-hold (S/H) is provided.

In the parallel embodiment, two or more S/Hs per output line, requiringone TFT per S/H, are addressed for writing on alternate lines andreading on other lines in accordance with the display pixel format andthe video input format. The output of the S/Hs are multiplexed onto oneoutput driver by additional TFTs, one per S/H, requiring four TFTs forthe minimum implementation.

For the series embodiment, the input S/Hs are loaded in succession afterwhich the stored data is loaded broadside into another parallel S/Hwhich functions as an analog register. The series embodiment reduces thedevice input capacitance and only requires two TFTs for the minimumimplementation but reduces the voltage to the driver since the charge onthe first S/H must also drive the second S/H without amplification. Thesecond TFT must be characterized by a low resistance for transferringthe charge in a short deadtime between switching since the first row ofTFTs cannot be permitted to receive signal again until the transfer hasbeen completed. The capacitors in the series S/H topology need only beof sufficient size to provide drive current for the duration of one linesince that is all the storage time that is needed. However, the presenceof two series stages tends to increase the switching noise. Thedouble-buffered S/H needs twice the capacitance since data loaded at thebeginning of one line must be retained through the end of the next line.

The design of the output drive stage must take into consideration anumber of criteria and limitations dictated by the requirements forintegration with the display. An essential feature of the output driverstage is that it must provide accurate output for any load whileremaining independent of TFT threshold voltage.

Digital and analog drivers have been proposed which use a capacitiveoutput drive. However, these prior art designs are non-scalable todifferent direct-view applications since the output capacitor must bemuch larger than the combined capacitance of the source line and pixelcapacitance (with one line of array TFTs on). Therefore, these prior artsource drivers are restricted to use with very small displays for eitherprojection or helmet-size direct viewing.

SUMMARY OF THE INVENTION

According to the present invention, an integrated analog source driveris provided which may be implemented using a minimal number of TFTs andcapacitors (14 NMOS TFTs and 3 capacitors in the preferred embodiment),and no resistors or other types of devices. The integrated analog sourcedriver of the present invention may be fabricated concurrently with theactive matrix devices of a display, without requiring any additionalprocess steps. The output impedance of the inventive integrated analogsource driver is low enough to drive a broad selection of displaysranging from projection/helmet displays to workstation displays.According to the present invention, the driver characteristics are madeindependent of TFT characteristics through the use of a novel circuitarchitecture.

The integrated analog source driver of the preferred embodiment has twoS/H stages, one being connected to the true analog video signalcontaining standard RGB-type information, etc., and the other beingconnected to the inverted analog video signal. Adjacent video lines areconnected to opposite polarity video signals, and are switched aftereach line in such a way that the polarity of the video may be made toalternate in both row and column directions in the manner of acheckerboard, to minimize the DC signal component tending to dissociatethe LCD fluid and polarize the alignment layer (although alternatives tothe checkerboard polarity method may be utilized such as row inversion,column inversion, frame inversion, etc.). This alternation is furtherreversed every frame. The two S/H outputs per source driver aremultiplexed onto the gate of a source follower TFT such that while oneS/H is driving the output stage with the signal for the current line,the other S/H is acquiring the signal for the next line. The outputstage is a source follower which drives one active matrix source lineand is the top TFT in a totem-pole output stage. The bottom device ofthe totem pole is a reset TFT whose drain is also connected to theoutput source line. The source follower and reset TFTs are preventedfrom conducting current at the same time by switching off the sourcefollower either by a second gate or by removing its supply voltage whilethe reset TFT is conducting.

An autozero circuit is connected to the output stage for cancelling theeffect of TFT threshold voltage on the output source follower TFT. Theautozero circuit operates such that the output voltage is driven to thesignal level and then reset to the most negative voltage after theactive matrix is disabled (by driving all matrix gates to the inactivestate). The source follower gate is then grounded and the output voltageat the source line is stored on a capacitor whose other terminal isgrounded. The voltage on this capacitor is reversed by grounding theopposite side and this voltage is then placed in series with the S/Hcapacitor which is currently driving the output. The output is resetagain and then the S/H gate signal is connected in series with theautozero value in the capacitor. This combined signal is applied todrive the source follower for the next line. Autozeroing in this fashioncounteracts the offset of the output source follower TFT so thatvariations in the threshold voltage of the TFT do not affect the output.Since the gain in a follower stage is slightly less than unity,regardless of TFT variations, no gain calibration is required.

BRIEF INTRODUCTION TO THE DRAWINGS

A detailed description of the preferred embodiment is provided hereinbelow with reference to the drawings, in which:

FIG. 1 is a schematic diagram of an integrated analog source driveraccording to the present invention; and

FIG. 2 is a timing diagram showing sequence of operation of the elementsof the driver shown in FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The integrated analog source driver shown in FIG. 1 uses adouble-buffered input S/H (Q1, C1 and Q3, C2) driven by a shift register(not shown, but being of well known design). The shift registergenerates the Q1 and Q3 gating signals shown in FIG. 2. When either oneof the TFTs Q1 or Q3 is conducting, the corresponding one of the analogvideo signals (+VIDEO, -VIDEO) is sampled via the associated storagecapacitor C1 or C2. However, in order to sample the signals onto C1 orC2, TFTs Q11 or Q12, respectively, must be conducting so as to groundthe lower terminal of the capacitors. The double-buffered S/H outputsare multiplexed to the driver stage (Q14 and Q15) by two TFTs Q2 and Q4,in accordance with the timing signals for Q2 and Q4 as shown in FIG. 2.A reset TFT Q13 is required to reset the output signal in the presenceof large pixel capacitance on the output (SOURCE LINE).

The stored charge on C1 or C2 must have added to it a further chargeequal to the threshold voltage (V_(t)) of the source follower Q14 tocancel the effects of the threshold voltage, and thereby eliminatethreshold dependent non-uniformities superimposed on the signal appliedto the SOURCE LINE which would otherwise occur. Therefore, as discussedin greater detail below, an autozero circuit is incorporated for biasingcapacitors C1 and C2 via series connected capacitor C3 with a sufficientcharge to cancel the TFT threshold voltage (V_(t)) of the sourcefollower TFT Q14.

Thus, as shown in FIG. 2, there are four operational phases per videoline. First, the true (or inverted) video signal is applied to theSOURCE LINE (denoted as LINE O/P in FIG. 2). The gates of the AMLCD TFTarray switch on and off in the usual manner for the duration of the LINEO/P, for generating the required video signal via the array pixelelectrodes (not shown) which are connected to the SOURCE LINE.

Next, a first reset (denoted as RST in FIG. 2) is performed, followed bythe aforementioned autozero function (AZ in FIG. 2), and finally asecond short reset (RST) is performed, as discussed in greater detailbelow.

The double-buffered input S/H design reduces insertion loss and inputvoltage requirements, and permits line-by-line video inversion withoutextra switching. Pixel-by-pixel inversion is effected by driving thealternate S/Hs in the same row by antiphase video sources (+VIDEO and-VIDEO). No external inversion is required.

As indicated above, the driver stage comprises a source follower TFT(Q14), shown in FIG. 1 with an upper cascode gate (Q15) which is usedfor switching only. As an alternative, two separate TFTs Q14 and Q15 maybe used, or the V⁺ supply may be gated externally without requiring TFTQ15. Also, as discussed above, a reset TFT (Q13) is connected to theoutput (SOURCE LINE) to pull down the output line voltage to a minimumvoltage (V⁻) before and after autozero capacitor C3 is charged. Thefirst and second resets occur during the "deadtime" between LINE O/Pphases, and must be able to discharge the SOURCE LINE capacitance(typically several hundred pF). Since each pixel of the AMLCD is drivenby a video signal of opposite polarity to the one above (or before) it,it is possible for a maximum signal voltage to be followed by a minimumvoltage. Therefore, the first reset must be of sufficient duration topermit the SOURCE LINE capacitance to be discharged. The second reset(after autozero) is only half as long as the first reset since theSOURCE LINE voltage is below ground voltage after autozeroing. Since thedesign includes no resistors, the capacitive load is reset to thenegative rail (V⁻), and after RST signal is released, the sourcefollower drives the output (SOURCE LINE) to the sampled signal level.

The autozero circuit shown in FIG. 1 uses eight TFTs (Q5, Q6, Q7, Q8,Q9, Q10, Q11 and Q12) and one capacitor (C3). In operation, the driverinput is grounded by switching TFT Q5 on with an autozero (AZ) signal.In response, the output voltage (which is negative and approximatelyequal in magnitude to the TFT threshold voltage V_(t)) is stored oncapacitor C3 as a result of the AZ signal also switching TFTs Q7 and Q8on while the unzero signal (UNZ) maintains TFT Q6 off and logic low gatesignals maintain TFTs Q9 and Q10 in the off state. Accordingly, thepolarity of the stored voltage is such that the capacitor plateconnected to Q6 and Q7 is negative relative the plate connected to Q8,Q9 and Q10. Capacitor C3 is then electrically disconnected by switchingoff Q7 and Q8 (falling edge of AZ). Capacitor C3 is then electricallyreconnected to the circuit by switching on TFT Q6 (rising edge of UNZ)and one of either Q9 or Q10 (in FIG. 2, Q9 is shown being switched on).The plate connected to Q6 and Q7 remains electrically negative relativeto the plate connected to Q8, Q9 and Q10, but is electrically connectedin such a way that the threshold voltage V_(t) is added rather thansubtracted from the signal stored on C1 or C2. Since the gain of thesource follower is approximately unity, when voltage is inverted andplaced on the gate of follower transistor Q14 by TFT Q6 and one of TFTQ9 or Q10, it drives the output (SOURCE LINE) to zero volts regardlessof the actual value of V_(t).

As can be seen from FIG. 2, the switching required to operate the driverof the present invention is somewhat complex since the basic video S/Hcircuitry requires four TFTs (Q1, Q2, Q3 and Q4) plus one transistor(Q5) to ground the gate of source follower TFT Q14, and double-throwswitching of the bottom terminals of S/H capacitors C1 and C2 betweenground and the autozero capacitor C3 through Q9, Q10, Q11 and Q12. Eachside of the double buffer input must be connected separately to theautozero capacitor C3 since when one of C1 or C2 is connected to theautozero capacitor C3 the other S/H capacitor must be grounded to storethe input video signal. The TFTs (Q5-Q12) and capacitor C3 used forautozeroing are preferably the same (small) size as the S/H TFTs andcapacitors.

The total parts count of 14 (or 15) TFTs and 3 capacitors forimplementing the all-purpose analog driver of FIG. 1 compares favourablywith the 21 TFTs and 8 capacitors used in the prior art 4-bitnon-scalable switched-capacitor driver described in the article ofSchleupen, K., et al., discussed above. It should be noted that thisparts count does not include the TFTs used in the shift register (notshown) for addressing the S/H inputs nor the gates (not shown) used togenerate the Q1 and Q3 switching waveforms. Depending on the structureof the input S/H circuits (there may be more than two S/H circuits perchannel), a S/H circuit fed by the video signal of either polarity mustbe activated for each input. Which input S/H circuit is activateddepends on the polarity of the signal to be applied to the output. Inthe embodiment shown, either Q1 or Q3 would be selected. Accordingly,this may be effected by using a pair of shift registers with outputgating that selects which one of Q1 or Q3 will be switched on. Thisselection logic would require the sampling pulses to be demultiplexedeither at the shift register output or by the use of cascode TFTs asinput sampling devices. The former is preferable since gating at theshift register output does not degrade signal integrity whereasdouble-gate devices for Q1 and Q3 would likely inject extra switchingnoise. The shift register and the additional switching gates are notshown because they form part of the prior art, they are ancillary to anddo not form a part of the actual circuit of the invention as set forthin the claims below.

In summary, the integrated analog source driver of the present inventionovercomes the advantages of prior art p-Si and CdSe integrated sourcedriver designs which use capacitive drives and which are only suitablefor small displays, by providing a driver which is suitable as a"one-size-fits-all" solution for any size of display. It is believed tobe hitherto unknown in the art to use autozeroing as a means ofobtaining linear current amplification with independence from TFTthreshold characteristics. Furthermore, the driver is processed (ie.fabricated) concurrently with the array TFTs and therefore requires nonew processes or extra processing steps and current amplification isprovided. The small number of circuit elements (TFTs and capacitors--noresistors) allows the driver of the present invention to be made smallerthan existing drivers for use with small pixel pitches, which is animportant commercial consideration for high-resolution helmet andprojection display applications. The output impedance of the integrateddriver of the present invention is sufficiently low to drive the sourceline capacitance of a large display panel, and the driver inputimpedance is high. The driver speed is compatible with video inputs. Forwideband video, a plurality of separate inputs may be provided to reducebandwidth requirements. Also, video inversion may be effected in astraightforward manner

Other embodiments and variations of the invention are possible Forexample, the input circuitry may be made according to a variety ofdesigns to suit different input and pixel arrangements and polarityschemes. Also, the driver can be fabricated from a number of suitablesemiconductor materials, such as amorphous silicon, polycrystallinesilicon, single-crystal silicon, gallium arsenide, germanium-silicon aswell as cadmium selenide. All such alternative embodiments andvariations are believed to be within the scope of the present inventionhaving regard to the claims appended hereto.

I claim:
 1. A source driver for an active matrix liquid crystal display,comprising:a) a sample-and-hold circuit for sampling successive lines ofan input video signal; b) a source follower for applying said successivelines of said input video signal sampled by said sample-and-hold circuitto successive source lines of said active matrix crystal display, saidsource follower being characterized by a predetermined thresholdvoltage; c) a reset circuit for resetting said successive source linesafter respective ones of said successive lines of said input videosignal; and d) an autozero circuit for cancelling said threshold voltagefrom said video signal so that variations in the threshold voltage donot affect the video signal applied to said successive source lines bydriving an output voltage to a level of said video signal level and thenresetting said output voltage to a negative voltage after said activematrix liquid crystal display is disabled.
 2. The source driver of claim1, wherein said sample-and-hold circuit further comprises a firstsample-and-hold stage for receiving said video signal and a secondsample-and-hold stage connected in parallel with said firstsample-and-hold stage for receiving an inverted version of said videosignal, said first sample-and-hold stage being addressed for samplingalternate ones of said lines of video signal and said secondsample-and-hold stage being addressed for sampling intermediatealternate ones of said lines of video signal.
 3. The source driver ofclaim 2, further comprising a multiplexer for applying the oppositepolarity video signals sampled by said sample-and-hold circuit to saidsource follower such that the polarity of the video signal alternates inboth row and column directions of said active matrix liquid crystaldisplay in the manner of a checkerboard.
 4. A source driver for anactive matrix liquid crystal display, comprising:a) a sample-and-holdcircuit for sampling successive lines of an input video signal, saidsample-and-hold circuit including a first sample-and-hold stage forreceiving said video signal and a second sample-and-hold stage connectedin parallel with said first sample-and-hold stage for receiving aninverted version of said video signal, said first sample-and-hold stagebeing addressed for sampling alternate ones of said lines of videosignal and said second sample-and-hold stage being addressed forsampling intermediate alternate ones of said lines of video signal, saidfirst sample-and-hold stage comprises a first capacitor and a first pairof switching transistors connected to opposite terminals of said firstcapacitor for gating said video signal into said first capacitor, andsaid second sample-and-hold stage comprises a second capacitor and asecond pair of switching transistors connected to opposite terminals ofsaid second capacitor for gating said inverted version of said videosignal into said second capacitor; b) a source follower for applyingsaid successive lines of said input video signal sampled by saidsample-and-hold circuit to successive source lines of said active matrixcrystal display, said source follower being characterized by apredetermined threshold voltage; c) a reset circuit for resetting saidsuccessive source lines after respective ones of said successive linesof said input video signal; and d) an autozero circuit for cancelingsaid threshold voltage from said video signal so that variations in thethreshold voltage do not affect the video signal applied to saidsuccessive source lines; and e) a multiplexer for applying the oppositepolarity video signals sampled by said sample-and-hold circuit to saidsource follower such that the polarity of the video signal alternates inboth row and column directions of said active matrix liquid crystaldisplay in the manner of a checkerboard.
 5. The source driver of claim4, wherein said multiplexer comprises a first additional switchingtransistor for gating said alternate ones of said lines of video signalstored on said first capacitor to said source follower while said secondsample-and-hold stage samples said intermediate alternate ones of saidlines of video signal, and a second additional switching transistor forgating said intermediate alternate ones of said lines of video signalstored on said second capacitor to said source follower while said firstsample-and-hold stage samples said alternate ones of said lines of videosignal.
 6. The source driver of claim 5, wherein said source followerfurther comprises a linear transistor having a signal input connected tosaid first and second additional switching transistors, a first signalterminal connected to a source of positive voltage supply and a secondsignal terminal connected to said source lines.
 7. The source driver ofclaim 6, wherein said reset circuit further comprises a third additionalswitching transistor connected in totem pole configuration between saidlinear transistor and a source of negative voltage supply.
 8. The sourcedriver of claim 7, wherein said autozero circuit further comprises afourth additional switching transistor for grounding said signal inputof said linear transistor, fifth and sixth additional switchingtransistors connected to first and second terminals of a third capacitorfor storing the output voltage on said source lines on said thirdcapacitor, said output voltage being equivalent to said thresholdvoltage, a seventh switching transistor connected to said first terminalof said third capacitor and eighth and ninth switching transistors eachconnected to the second terminal of said third capacitor andrespectively to said first capacitor and said second capacitor forconnecting said third capacitor in series with respective ones of saidfirst and second capacitors thereby cancelling said threshold voltage.9. A source driver for an active matrix liquid crystal display,comprising:a) a sample-and-hold circuit for sampling successive lines ofan input video signal; b) a source follower for applying said successivelines of said input video signal sampled by said sample-and-hold circuitto successive source lines of said active matrix crystal display, saidsource follower being characterized by a predetermined thresholdvoltage; c) a reset circuit for resetting said successive source linesafter respective ones of said successive lines of said input videosignal; and d) an autozero circuit for canceling said threshold voltagefrom said video signal so that variations in the threshold voltage donot affect the video signal applied to said successive source lines;wherein said sample-and-hold circuit comprises a first sample-and-holdstage for receiving said video signal and a second sample-and-hold stageconnected in parallel with said first sample-and-hold stage forreceiving an inverted version of said video signal; and wherein saidfirst sample-and-hold stage comprises a first capacitor and a first pairof switching transistors connected to opposite terminals of said firstcapacitor for gating said video signal into said first capacitor, andsaid second sample-and-hold stage comprises a second capacitor and asecond pair of switching transistors connected to opposite terminals ofsaid second capacitor for gating said inverted version of said videosignal into said second capacitor.
 10. The source driver of claim 9wherein said first sample-and-hold stage is addressed for samplingalternate ones of said lines of video signal and said secondsample-and-hold stage is addressed for sampling intermediate alternateones of said lines of video signal.
 11. The source driver of claim 10,further comprising a multiplexer for applying the opposite polarityvideo signals sampled by said sample-and-hold circuit to said sourcefollower such that the polarity of the video signal alternates in bothrow and column directions of said active matrix liquid crystal displayin the manner of a checkerboard.
 12. The source driver of claim 11,wherein said multiplexer comprises a first additional switchingtransistor for gating said alternate ones of said lines of video signalstored on said first capacitor to said source follower while said secondsample-and-hold stage samples said intermediate alternate ones of saidlines of video signal, and a second additional switching transistor forgating said intermediate alternate ones of said lines of video signalstored on said second capacitor to said source follower while said firstsample-and-hold stage samples said alternate ones of said lines of videosignal.
 13. The source driver of claim 12, wherein said source followerfurther comprises a linear transistor having a signal input connected tosaid first and second additional switching transistors, a first signalterminal connected to a source of positive voltage supply and a secondsignal terminal connected to said source lines.
 14. The source driver ofclaim 13, wherein said reset circuit further comprises a thirdadditional switching transistor connected in totem pole configurationbetween said linear transistor and a source of negative voltage supply.15. The source driver of claim 14, wherein said autozero circuit furthercomprises a fourth additional switching transistor for grounding saidsignal input of said linear transistor, fifth and sixth additionalswitching transistors connected to first and second terminals of a thirdcapacitor for storing the output voltage on said source lines on saidthird capacitor, said output voltage being equivalent to said thresholdvoltage, a seventh switching transistor connected to said first terminalof said third capacitor and eighth and ninth switching transistors eachconnected to the second terminal of said third capacitor andrespectively to said first capacitor and said second capacitor forconnecting said third capacitor in series with respective ones of saidfirst and second capacitors thereby canceling said threshold voltage.